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Altera_Forum
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16 years ago

Using Gigabit ethernet chip, do I need to ccontrol the data path length?

Hi, In one of our CIII board, we need to use 88E1111. My question is: do we need to make sure the length of all data line(TXD, RXD) are the same in order to achieve maximum data rate? H...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

"the same in order" sounds reasonable. Check the chip specification for tolerable delay skew with either GMII or RGMII interface and calculate the setup and hold margin depending on the FPGA side of the interface. I would expect, that a trace length difference up to 1-2" can be tolerated in most designs.