User controlled burst refresh

Hi,

I have a problem regarding DDR3 EMIF IP can't bursting user control refresh.

I am debugging my EMIF test design on Cyclone 10 GX development board.

The situation is that it takes long time to get mmr_refresh_ack response.

Below is my environment:

Quartus Prime Pro 23.2 on Windows 11

External Memory Interfaces Intel Cyclone 10 FPGA IP, altera_emif_c10 19.1.1

Cyclone 10 GX FPGA Development Kit (Power Solution 1) DK-DEV-10CX220-A

Cyclone 10 GX 10CX220YF780E5G

First of all, I have a question about the description of the user guide.

I would like to fix my design after question was solved.

I am referring External Memory Interfaces Cyclone 10 GX FPGA IP User Guide Updated for Quartus Prime Design Suite: 24.1 IP Version: 19.1.2.

1. In page 84, Table 4.4.13 for mmr_refresh_req states that Controller clears this bit to 0 when the refresh is executed.

This is inconsistent for the description:

Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage:

The waveform instruct user to clear mmr_refresh_req before set mmr_refresh_req again at reference time (5).

I guess this waveform explains back-to-back user controlled refresh so, the next refresh request is expected tRFC after reference time (4).

My question is:

Should I clear the mmr_refresh_req register before back-to-back next refresh request?

2. In page 223,

---

Note: If you enable the auto-precharge control, you must ensure that the average periodic

refresh requirement is met, because the controller does not issue any refreshes until

you instruct it to.

---

What happens if I disable the auto-precharge control?

In this case, are both IP planned refresh and user controlled refresh happens?

3. There are two enable user refresh controls in the user guide:

1) IP parameter of Enable User Refresh Control

2) cfg_user_rfsh_en register inside the IP

What is the relationship of them?

Does the IP parameter define initial state of cfg_user_rfsh_en register?

Is the logical AND condition needed for the user controlled refresh?

4. In page 78, table 4.4. Cyclone 10 GX Memory Mapped Register (MMR) Tables:

The cfg_user_rfsh_en register is missing.

Do I need to handle this register?

Masaru