Forum Discussion
User controlled burst refresh
- 1 month ago
I found three incorrect explanations of section 9.4.6 User-Controlled Refresh.
1. Page 223, Note:, "If you enable the auto-precharge control,..."
should be "If you enable the user controled refresh,...".2. Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage,
Step 1 to write the cfg_user_rfsh_en register should not be done.
If we write to the register, we do not receive acknolegement for a long time at step 3.3. Page 223, Fighre 87, the tRFC mesurement should start with timing (2) not with (4).
By my interpretations, my design works fine for back to back user contlloled refresh.
altera should fix section 9.4.6 User-Controlled Refresh.
Masaru
For my point 4, you said:
>I don't think you need to enable it from the user logic.
Is "it" referring cfg_user_rfsh_en register?
Hi MamaSaru ,
"Is "it" referring cfg_user_rfsh_en register?"
-Yes
Maybe you also can try to assert read for one clock cycle only instead of assert read until readdatavalid.
Regards,
Adzim
- MamaSaru1 month ago
Occasional Contributor
Adzim,
For my point 4 and 1, altera should provide correct information to users.
If the cfg_user_rfsh_en register is not needed to access from user logic as you said,
altera should revise Page 223, Section 9.4.6.1 up to correct waveform and put its explanation.
I do not wat to try something and discard it back and forth.
Does someone from altera can answer my question points?
Regards,
Masaru