Occasional Contributor
Occasional ContributorHi Adzim,
Thank you for your reply.
1. >- No the IP should handle it.
So, the section "9.4.6.1. Back-to-Back User-Controlled Refresh Usage" should be revised
not to clear the mmr_refresh_req register.
2. >- You should control the refresh since the IP doesn't issue the refresh if user controlled refresh is enabled.
No, original statement said, "If you enable the auto-precharge control,".
Is this statement correct?
3. >- You don't have to care about that. Only use the MMR interface.
Do you mean the Enable User Refresh IP parameter doesn't affect at all?
Can I run user control refresh under IP parameter is off?
4. - No need.
Do you mean I don't need to handle cfg_user_rfsh_en register?
I am confused about your answer.
Masaru
Regular ContributorHi Masaru,
When user control refresh is enabled, user has complete control and responsible to provide sufficient refresh to memory.
The statement in EMIF UG mentioned it here: https://docs.altera.com/r/docs/683663/24.1/external-memory-interfaces-cyclone-10-gx-fpga-ip-user-guide/intel-cyclone-10-gx-emif-ip-ddr3-parameters-controller
The IP should enable the user control refresh already.
I don't think you need to enable it from the user logic.
Regards,
Adzim
Occasional Contributor
For my point 4, you said:
>I don't think you need to enable it from the user logic.
Is "it" referring cfg_user_rfsh_en register?
Regular ContributorHi MamaSaru ,
"Is "it" referring cfg_user_rfsh_en register?"
-Yes
Maybe you also can try to assert read for one clock cycle only instead of assert read until readdatavalid.
Regards,
Adzim
Occasional ContributorAdzim,
For my point 4 and 1, altera should provide correct information to users.
If the cfg_user_rfsh_en register is not needed to access from user logic as you said,
altera should revise Page 223, Section 9.4.6.1 up to correct waveform and put its explanation.
I do not wat to try something and discard it back and forth.
Does someone from altera can answer my question points?
Regards,
Masaru
