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Altera_Forum
Honored Contributor
11 years agoUser Auto-Refresh Conduit with hard memory Controller. Strange request behaviour?
Hi all, I have an FPGA application which needs the DDR3. I am able to write and read through the MPFE (Multi-Port Front End) but I have some criticial timing therefore I want to handle the refre...
Altera_Forum
Honored Contributor
11 years agoThanks four your reply.
Currently I am using a Cyclone V device. You need to keep in mind that this happens in simulation with ModelSim. When my custom logic tells me that every request is passed to the controller, I assert the request. Kept watching for an acknowledgment for about 5000 clock cycles and still no acknowledgment. If I use the oscillation on the request signal, which basically looks then like a half rate clock in the waveforms, I get the acknowledgment after 10 or 12 clock cycles. To me it looks like the controller is ignoring the first refresh requests because it needs to deal with the read and write requests. And it looks like the controller only checks for rising edges on the local_refresh_req signal, otherwise there would be no different behaviour between a constant high signal, which never leads to an acknowledgment, and a oscillating singal, which leads to many rising and falling edges on the req signal until the acknowledgment is received.