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aroturier's avatar
aroturier
Icon for New Contributor rankNew Contributor
5 years ago

Use internal oscillator as an input of ALTCLKCTRL IP MAX 10

Hi,

It is the first time i work with a FPGA from Intel (MAX10) and Quartus.

I would like to use ALTCLKCTRL IP in order to mux two clocks.

One is an external clock, the other one comes from the internal oscillator.

However, i got the following error message during my design synthesis :

Error (15660): inclk[0] port of Clock Control Block "clock_control:clock_contrtol_inst|clock_control_altclkctrl_0:altclkctrl_0|clock_control_altclkctrl_0_sub:clock_control_altclkctrl_0_sub_component|clkctrl1" is driven by int_osc:int_osc_inst|altera_int_osc:int_osc_0|wire_clkout, but must be driven by a clock pin

What I undestand with this message is I have to use a clock pin as an input of ALTCLKCTRL IP (as my external clock), but with the internal oscillator, I can't really use one.

Can you help me to handle this error ?

Regards,

Antoine

4 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Antoine,


    This message indicates that the specified inclk port of the specified Clock Control Block is driven by the specified illegal source. When the clkselect port is used, the inclk ports of a Clock Control Block must only be driven by clock pins or PLL clock outputs. The inclk[0] and inclk[1] need to be driven by pins and inclk[2] and inclk[3] need to be driven by a PLL output. In this case, you have to modify the design so that inclk port of the specified Clock Control Block is driven by the specified legal sources.

    Thanks


    Best regards,

    KhaiY


    • aroturier's avatar
      aroturier
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi,

      Thanks @KhaiChein_Y_Intel for the answer.

      I tried to use a PLL, whose the input pin is my internal oscillator.

      However, i still have an error message :

      Error (15065): Clock input port inclk[0] of PLL "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

      Does it mean I only can feed my PLL with an external clock signal through a non inverted input pin ?

      Is there really no way to use the internal oscillator as a PLL input ?

      Regards,

      Antoine

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Antoine,


    No. You have to modify the design so that the clock input port of the specified PLL is driven by a non-inverted input pin or another PLL.


    Thanks

    Best regards,

    KhaiY


  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


    Best regards,

    KhaiY