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aroturier's avatar
aroturier
Icon for New Contributor rankNew Contributor
5 years ago

Use internal oscillator as an input of ALTCLKCTRL IP MAX 10

Hi, It is the first time i work with a FPGA from Intel (MAX10) and Quartus. I would like to use ALTCLKCTRL IP in order to mux two clocks. One is an external clock, the other one comes from the ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Antoine,


No. You have to modify the design so that the clock input port of the specified PLL is driven by a non-inverted input pin or another PLL.


Thanks

Best regards,

KhaiY