Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Use EPCS1SI8N as memory

Hi all, For my project, I plan to use an EPCS1SI8N as an EEPROM memory for keeping data and only that. (I have another EPCS to program my FPGA). After launching the FPGA, it has two read...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I watched the code opeartion in a simulation and found that the asdi timing is not according to the SPI mode 0 or 3 requirements. Please read the Altera EPCS or third party SPI flash datasheets (e.g. Numonyx M25P10) thoroughly. ASDI has to be set before the rising DCLK edge, usually it's set on falling edge. There may be more issues, but the code can't work with the present SPI timing.