Uniphy DDR3 controller waitrequest simulation problem/How to simulate Uniphy memory

Hello,

Thanks for your answer, I have gone through the training course, tried generating an example design, it compiled and did the simulation. Unfortunately, as soon as I tried to compile the testbench generated by Qsys, it failed with the the error message:

"Altera DDR3 Memory Model for UniPHY does not support the QUARTUS_SYNTH fileset".

Then I tried downloading the simulation model from the vendor of the memory. However, the simulation model has SystemVerilog parts and thus the compiler of Quartus-Modelsim Starter Edition does not recognise some parts of it, so I cannot even try it out. I simply do not now where to get an usable model I can use for simulation. The problem is, that the SystemVerilog part is right in the memory model, not even in the testbench.

Where or how can I get a usable simulation model in this case?