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Honored Contributor
Honored ContributorUniphy DDR3 controller hold issue with Q10.1
Hi, I just upgraded to Quartus 10.1 and regenerated my Uniphy DDR3 controller cores. Now I get hold timing errors on the memphy_leveling_clk domain. Does anybody else see this problem? Any idea...
Altera_ForumHonored Contributor
Honored ContributorGot it fixed. For others having the same problem: You need to ensure (using assignments) the memphy pll clocks are routed using global clocks. If the Fitter picks regional clocks the hold slack worsens by about 300ps.
