Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Unexpected data write while connecting FPGA to PC via PCIe

Hello. I am tying to communicate between HostPC(Linux) and FPGA Board using PCI Express High Performance Reference Design (AN456). But I am observing unexpected data write to Endpoint memory on...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I'm also using chaining dma which is generated by pcie megacore function. According Ip compiler for user guider,the data is stored in shared memory in the Root Complex.But there many problems to find how the data are transmitted.