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Honored Contributor
Honored ContributorUnexpected data write while connecting FPGA to PC via PCIe
Hello. I am tying to communicate between HostPC(Linux) and FPGA Board using PCI Express High Performance Reference Design (AN456). But I am observing unexpected data write to Endpoint memory on...
Altera_ForumHonored Contributor
Honored ContributorAre they memory writes or IO writes? It might help if you post the bytes of the TLP from your signaltap trace.
