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Altera_Forum's avatar
Altera_Forum
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15 years ago

Unexpected data write while connecting FPGA to PC via PCIe

Hello. I am tying to communicate between HostPC(Linux) and FPGA Board using PCI Express High Performance Reference Design (AN456). But I am observing unexpected data write to Endpoint memory on...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Are they memory writes or IO writes? It might help if you post the bytes of the TLP from your signaltap trace.