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JuanEscobedo's avatar
JuanEscobedo
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6 months ago

Unexpected behavior of DDR3 controller on Arria V GZ when using manual refresh

deHello, I am using the DDR3 controller IP on an Arria V GZ FPGA and I am noticing a different behavior when issuing a refresh request using the manual refresh interface. When issuing the refresh a...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
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6 months ago

Hi Juan,


Do you have any feedback in this thread?


Regards,

Adzim


  • JuanEscobedo's avatar
    JuanEscobedo
    Icon for New Contributor rankNew Contributor
    5 months ago

    Hello Adzim,

    Yes, the ~1023 cycle refresh rate is to mee the timing of the memory.

    I changed the logic of my FSM a bit so that there is a gap, single clock, state between the read and write transactions and the code behaves as expected.

    Thanks for your support.

    Juan