Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Undesired (incorrect?) behavour of CVI AV-ST output

Hi, I have a video stream (BT1120) entering an FPGA through the CVI. The stream can be interrupted at any time (someone pulling out the plug). I have an internally generated "blue-screen" that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello Niki,

In my system the SDI IP is connected to the CVI.

I had similar problems with source disconnection but I suspected the SDI core and not the CVI. Finally I have concluded to the exact solution as yours "single clock mode", this solution solved my problems (that I thought was SDI core problems).

Now after I read your post I get a much better understanding, and I agree with your conclusions that this is CVI problem.

I was working on version 10.1.

Thank you for your detailed explanation.

BR,