Honored Contributor
Honored ContributorHi,
Thanks for the response! The simulation was with the switch, so, yes, the switch could influence the results. But since the Avalon ST inteface gives a full "picture" of what the CVI sees, it does not really matter what is connected to the CVI. The switch may cause a certain pattern of back-pressure that causes the CVI to fail, but that is exactly what I would like to investigate. If you look closely at the CVI_1 picture, you will see that just before the vid_locked signal goes low, the CVI is outputting valid data (you see the pulses on is_valid). The moment the vid_locked signal goes low, the CVI stops outputting valid data, while the ready line (is_ready) remains high - so there is no backpressure from the downstream switch. The is_valid output remain low until the is_locked line goes high again. As soon as new video data enters the CVI (the first 2/3 of the data entering the CVI is verticla sync data - I have reduced the active data to 32 lines in order to make the simulation run faster), the CVI just continues outputting valid data (see the pulses on is_valid) again. The error here is that the resulting video frame is much larger than the preceding control frame indicates, and contains data from two different video frames. And, if there was no more input data, the output of the CVI would still be halfway through the video frame, and this stalls the switch (and basically the whole video pipeline). The reason I am investigating this is because I am actually seeing it in my hardware - very reproduceable. I have already had to write my own switch so that I can implement work-arounds in the switch for this to force a switchover. If anybody can verify (or contradict) this behavour of the CVI in simulation I would be very grateful! Regards, Niki
