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Altera_Forum's avatar
Altera_Forum
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12 years ago

Two Avalon ST Interfaces comparison

Hello all,

First, I'm sorry if this is not the right forum to post such question !

Second, I desperately need your help !

I'm trying to compare two avalon streaming interfaces (one output from a vip frame buffer and the other from a scaler) with the same resolution ! My problem is how to make my component receives both frames at the same time (make both startofpacket signals asserted at the same time) ? Logically the scaler source (or my custom component 1st sink) should control the other sink (from frame buffer) but I couldn't make that happen !

Any suggestion would be appreciated !

PS : Can I modify the alpha blending mixer behavior to make it compare the 2 sinks ? Or is there any explanation on how does it behave ?

Thank you

21 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I don't know about the VIP components so I can't answer your PS question, but more generally if you want to compare two streams, you can use the ready signals on both your sinks to control the data traffic. If one of the streams is sending data before the other one, set its ready signal to 0 to block the stream, until you get the data from the other one.

    Please note that when doing something like that it is a good idea to have a buffer like a Avalon Stream FIFO if the source doesn't support back-pressure.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Daixiwen,

    Thank you for responding

    Both sources support back-pressure and the Frame Buffer is a passive component so it delivers data whenever the READY signal is asserted (otherwise it stalls). So I'm using an SCFIFO for the scaler sources and I'm trying to read it when the READY signal from the output and the VALID signal from the frame buffer are asserted ! But I still get a delayed data !

    Can I manage to control both sources without using a FIFO ?

    Do you have any example on how to stall a stream to a startofpacket of another stream ?

    thank you
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You should be able to keep the ready signals on both sinks to '0' and wait until both valid signals are asserted. Then you can read both sources simultaneously.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    So both sources won't deliver data until I assert the READY signal ? I thought that the data is delivered whenever the ready signal is '1' and not the opposite !

    thank you
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The data is transferred from the source to the sink when both the ready and the valid signals are '1'. The ready signal is controlled by the sink and the valid signal is controlled by the source, so that way both the sink and the source can control the data flow.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Still doesn't explain how to align both frames ! My idea is to deliver data from the SCALER output and whenever there is valid data I set the READY signal for the other sink to '1'

    First sink ==> scfifo ==> output

    --> here I assert the READY signal for the second sink if first_sink.valid = '1'

    I couldn't align both frames with this !

    can you suggest another technique ?

    thank you
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Could you show with a timing diagram the problem you are having aligning frames? As far as I know, what I described in# 4 (put BOTH ready signals to 0 and only put them to 1 when BOTH valid signals are 1) should work.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Just to be clear: Altera VIP Frame Buffer component will buffer entire frames, ping-pong, then output. So, you are looking at at least (1) frame quantum of delay between input and output side of Frame Buffer.

    Other than that, it should really be as simple as Daixiwen has already described.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    hi again

    @Ted : I know that there is at least 1 frame delay between the VIP FB input and output (I'm counting on that since I'm gonna compute the difference between an old and the current frame) and I spend a lot of time reading the vip user guide and the avalon spec so I'm pretty sure that what Daixiwen described should work. but it doesn't and it's driving me crazy ! I appreciate your help and I'm desperately in need of a solution

    @Daixiwen : I attached the signal tap screen shot :

    the two counters count the number of pixel delivered (first counter from the FB source | second counter from the fifo that receives the scaler output)

    I hope that would help you figure out my mistake

    PS : the used resolution is 800x600 so maximum count is 480000

    thank you a lot
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The only comment I have on the capture you just posted is that FRAME_COUNTER|CLR is not tracking EOP like NEW_COUNTER|CLR is.