Forum Discussion
Honored ContributorTutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master
Hi all,
I've put together a tutorial on how to use the Altera JTAG-to-Avalon-MM master and Altera Verification IP Avalon-MM BFM Master under both SOPC builder and Qsys. http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip) The tutorial walks the user through the creation of an SOPC or Qsys system design, and provides scripts that automate the re-generation of the system. The tutorial shows how to simulate using Modelsim-ASE, and shows how to communicate with the hardware using System Console, quartus_stp, and then how to run a TCP/IP server under System Console or quartus_stp, and then communicate with that server from client code written in Tcl/Tk (a simple GUI) and a command-line C interface. Let me know if you like it, or have feedback/suggestions on how to improve the document. Cheers, Dave119 Replies
Altera_ForumI am a relative newbie to FPGA and soft processor design. I am using a Cyclone III Development Kit and Quartus II v13.1. I was able to get through section 4 of the tutorial, but now I am stuck at trying to use System Console. I did have to modify the Qsys design and tcl script in ModelSim (as shown in the qsys_vip tutorial file) to get everything to run correctly. When I open System Console, there are red x boxes by the "connections" and "devices" items in the System explorer. When I try to run the master_write_32 command shown in Figure 13 of the tutorial pdf, I get the following error:
error: master_write_32: This transaction did not complete in 60 seconds. System Console is giving up. Does anyone know what the issue is and how to fix this? Erin- Altera_Forum
Judging by the message I'm guessing the master in the system accessed something that didn't respond or the address that was used didn't exist in the system (Qsys fabric doesn't have a timeout mechanism). I would start by looking at the Qsys design and make sure the address you are attempting to access is present in the system. If you are trying to access a custom IP core then I would double check the implementation against the Avalon specification to make sure the logic is designed within spec.
- Altera_Forum
Hi Erin,
--- Quote Start --- When I open System Console, there are red x boxes by the "connections" and "devices" items in the System explorer. --- Quote End --- Sorry to ask the obvious, but did you download the design using the Quartus Programmer first, and then start SystemConsole? Cheers, Dave - Altera_Forum
Dave-
Yes I meant to mention that I did download the design first. Erin - Altera_Forum--- Quote Start --- Judging by the message I'm guessing the master in the system accessed something that didn't respond or the address that was used didn't exist in the system (Qsys fabric doesn't have a timeout mechanism). I would start by looking at the Qsys design and make sure the address you are attempting to access is present in the system. If you are trying to access a custom IP core then I would double check the implementation against the Avalon specification to make sure the logic is designed within spec. --- Quote End --- As far as I can tell, the addresses seem right (address for the LEDs is 0x0 and I'm trying to write to that address). Can you give any advice about which specs I should check for the LED connections? It's just a PIO set for output with a bit width of 8. Erin
- Altera_Forum
Hi Erin,
--- Quote Start --- Yes I meant to mention that I did download the design first. --- Quote End --- Could you post a screen shot of SystemConsole. I'd like to see what the messages are. You can email it to me directly if you like. Just email it to my forum name. Cheers, Dave - Altera_Forum--- Quote Start --- Could you post a screen shot of SystemConsole. I'd like to see what the messages are. --- Quote End --- Yes I will do that later this evening. The computer on which I'm running the Quartus II is not currently connected to the internet. Thanks for being willing to help. Erin
- Altera_Forum
Just to report back to this thread, I was eventually able to get my design to work and get the board communicate with System Console, with Dave's help over email. The issue seems to have been that my CPUreset was being held low (which means reset the system) and so was continually being reset. Once I inverted this signal, the board could communicate with my laptop via System Console just fine.
Thanks all, Erin - Altera_Forum
Quick question: I've read your nice tutorial with great interest. But I did not find any discussion relating to practical bandwidth. On a DE0-nano board, would this avalon/usb blaster interface support an average rate of 2 MB/s from board to host?
- Altera_Forum--- Quote Start --- Quick question: I've read your nice tutorial with great interest. But I did not find any discussion relating to practical bandwidth. On a DE0-nano board, would this avalon/usb blaster interface support an average rate of 2 MB/s from board to host? --- Quote End --- Sure, I've got lots of documents ... https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html The JTAG interface performance is documented in altera_jtag_to_avalon_analysis.pdf The performance is only about 600kB/s. You can use an FTDI device, check out ftdi.pdf (60MB/s for their HS devices) and ftdi_spi.pdf (2MB/s = 16Mbps serial data rate ... might be a bit fast). Take a read of those docs, and ask questions. Cheers, Dave
