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Altera_Forum
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14 years ago

Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

Hi all, I've put together a tutorial on how to use the Altera JTAG-to-Avalon-MM master and Altera Verification IP Avalon-MM BFM Master under both SOPC builder and Qsys. http://www.ovro.cal...
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Altera_Forum
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11 years ago

I am a relative newbie to FPGA and soft processor design. I am using a Cyclone III Development Kit and Quartus II v13.1. I was able to get through section 4 of the tutorial, but now I am stuck at trying to use System Console. I did have to modify the Qsys design and tcl script in ModelSim (as shown in the qsys_vip tutorial file) to get everything to run correctly. When I open System Console, there are red x boxes by the "connections" and "devices" items in the System explorer. When I try to run the master_write_32 command shown in Figure 13 of the tutorial pdf, I get the following error:

error: master_write_32: This transaction did not complete in 60 seconds. System Console is giving up.

Does anyone know what the issue is and how to fix this?

Erin