Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

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Say I take your example design with the ram, leds and buttons, and instead of buttons I use switches.

I run this design on two boards.

On one board I put the switch to high / one, meaning Master.

On the other board I put the switch to low/zero, meaning Slave.

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I have a similar setup with two Stratix IV GX Development kits.

The first thing I did was download FTDI's FT_PROG tool

http://www.ftdichip.com/support/utilities.htm

and I reprogrammed the Serial Number in the on-board USB-Blaster to have a unique value for each board, eg., S4GXDK01 and S4GXDK02. This ensures that Windows does not have issues when seeing two devices attached with the same USB serial numbers (in my experience all boards ship with a common serial number).

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I connect two usb-byteblaster to my pc and start System Console

Situation 1:

How do I:

- Scan for all available jtag2avalon master?

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The Tcl code in jtag_open ...

#  Get the list of masters
	set masters 
	if { == 0} {
		error "Error: No JTAG-to-Avalon-MM device found!"		
	}
		
#  Access the first master in the masters list
	set jtag(master) 
	open_service master $jtag(master)

Always accesses the first master in the list. In your code, you would modify this code to be something like

1. Add an argument which is the switch ID, eg., 0 or 1

2. Has the switch ID to master index mapping been created? If no, go to step 3, else go to step 4

3. Identify the two boards

- Open the first master, read its ID switch setting, store that info in the jtag global

- Open the second master, read its ID switch setting, store that info in the jtag global

4. Based on the switch ID argument, open_service on the master

Its been a while since I've played with my hardware setup, but I recall that System Console did not allow multiple JTAG masters to be accessed at the same time, i.e., you had to close one before opening the other. To deal with that, your JTAG read/write procedures need an extra argument, i.e., the master index, and then inside the read/write procedures you need to open the master perform the read/write, and then close the master.

In Tcl you can use a default value, eg.,

proc jtag_read {addr {master 0}} {
#  Read from addr on JTAG master 0 by default
}

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Situation 2:

This should be dynamic.

When I have this running, I want to be able to switch both boards in the other mode.

Meaning, the master becomes slave, and the slave becomes master.

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If you want it to be dynamic, then the mapping between ID and master would not be cached as described above, but determined for every access, i.e., read/write would be

1. Open the first master, is it the correct ID? Yes, go to step 3

2. Open the second master, is it the correct ID? (It should be)

3. Perform the read/write

4. Close the master

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I would like to run the same script without modifying it, and detect the new master and new slave board. Is that possible?

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Once you have modified the read/write procedures to open, detect the board, perform the read/write, and then close the board, then yes, this is all automated.

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Situation 3:

Now I start debugging, and add sometimes a NIOS with a jtag_uart, sometimes signaltap, sometimes both and sometimes none.

Can this script then still identify the jtag2avalon master and detect the master board and the slave board?

I assume that the nios has certain "jtag_identifier_code", and the signaltap as well.

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You'll have to try it and see.

I've had problems initializing SignalTap II triggers if I do not first "open" the JTAG master that is the source of the trigger, eg., it writes to a particular location.

Cheers,

Dave

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How do I:

- Scan for all available jtag2avalon master?

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This code should do it

foreach m  {
  array set info 
  puts "Found master at $info(FULL_HPATH)"
}

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- How do I assign a tcl variable MASTER, to the board that has the switch to one? So that I can use that MASTER in my other procedures for doing master_functions. For example "lit led 0 if you are a master board"

- And the same question for the slave.

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I assume you have a PIO slave which can read the value of the switch, and that this slave is mastered by an altera_jtag_avalon_master or altera_usb_debug_master.

Maybe something like this (I think I got the brackets right but please check):

foreach m  {
  array set info 
  if {$info(FULL_HPATH) == "my|expected|hpath"} {
    set mm 
    set v 
    if {$v == 1} {
      set master_on_master_board $m
    } else {
      set master_on_slave_board $m
    }
    close_service master $mm
  }
}

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Situation 2:

This should be dynamic.

When I have this running, I want to be able to switch both boards in the other mode.

Meaning, the master becomes slave, and the slave becomes master.

I would like to run the same script without modifying it, and detect the new master and new slave board. Is that possible?

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Yes, this is possible, you'll need to keep reading from the PIO slaves and arrange to swap your masters over when the roles change. The Tcl after (http://www.tcl.tk/man/tcl8.5/tclcmd/after.htm) command can be used to do this sort of thing (but make sure you have a way to cancel the after).

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Situation 3:

Now I start debugging, and add sometimes a NIOS with a jtag_uart, sometimes signaltap, sometimes both and sometimes none.

Can this script then still identify the jtag2avalon master and detect the master board and the slave board?

I assume that the nios has certain "jtag_identifier_code", and the signaltap as well.

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Each debug node has an identifier code which is used by the tools to work out which drivers need to be used to control it. SignalTap, JTAG UART, Nios II processor, JTAG debug link etc all have different IDs.

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Thanks! When was this function introduced (which Quartus release?)?

I doubt that it will be faster at the JTAG layer (since the JTAG traces show that master_read/write_memory are as efficient as possible), but at least it saves Tcl performing binary->string and string->binary conversions.

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It was first introduced in ACDS 12.1 I think.

Tcl is actually pretty good at conversions providing you use the right data structures. Where master_read_to_file and write_from_file really win is that they can do overlapped I/O (starting the second transfer while the hardware is processing the first one). For big transfers this hides the latency of the transfer and leads to a big performance improvement.

Out of interest, which tool are you using for your JTAG tracing?

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Out of interest, which tool are you using for your JTAG tracing?

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The JTAG traces in this analysis document are from SignalTap II

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip

Cheers,

Dave

Hi wombat,

master_get_info in your code doesn't work.

foreach m  {
  array set info 
  puts "Found master at $info(FULL_HPATH)"
}

When I type

% info commands master*

I get

master_read_memory master_write_from_file master_write_8 master_write_memory master_read_8 master_read_to_file master_read_16 master_write_16 master_read_32 master_write_32
%

What should this be?

Rgds,

Kimberley

Folks,

Sorry for the late reply, but just to let you know I've got it working.

I can now recognize the two phy's on the two boards.

Thanks again for all the support.

Rgds,

Kimberley

Thank you very much for this tutorial. It got me pretty far. However, I did this in Quartus II 13.0 sp1 and there are some differences, two of which result in errors. I didn't go through the SOPC Builder chapter since that tool isn't available anymore.

1. There are 33 warnings, not 3, when generating the Verilog files in Qsys. These are all Warning: qsys_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)". According to support solution spr371633 (http://www.altera.com/support/kdb/solutions/spr371633.html), these can be ignored.

2. The logic element counts are different (e.g. 1106 at the top level, not 1058). I suppose Altera changed the library components.

3. The Quartus II Handbook is different (e.g. the system console commands in table 10-3 mentioned in section 5.1 is on pages 10-9 through 10-11 of version 13.0 of the handbook).

4. When compiling the simulations, the vlog command's -L argument that worked for me is libraries/altera_avalon_vip_pkgs_lib, not qsys_system_bfm_master.

5. $TUTORIAL/hdl/qsys_system/scripts/sim.tcl contains the above error.

Section 4.5.1 talks about generating the code but I almost didn't do it because that discussion is formatted as regular text. All of the other directions are given in a list format.

The tutorial says nothing about how to use Quartus II to program the device. Perhaps you can add something about programming?

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Thank you very much for this tutorial. It got me pretty far.

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Great!

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However, I did this in Quartus II 13.0 sp1 and there are some differences, two of which result in errors. I didn't go through the SOPC Builder chapter since that tool isn't available anymore.

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Darn! I guess its time for me to revise the tutorial ... its been on my TODO list for a while :)

I'll take a look at it this week.

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The tutorial says nothing about how to use Quartus II to program the device. Perhaps you can add something about programming?

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Ok, I'll add a walk through.

Cheers,

Dave

I haven't had a chance to revise the tutorial yet, however, I did have a look at resolving the issues with Modelsim simulation.

The Qsys Verification IP Suite zip file (qsys_vip.zip) in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32952&page=3

walks through the simulation of a Qsys system under Quartus 12.1sp1 and 13.1.

Cheers,

Dave