Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

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First of all, thank you for putting this tutorial together. It's very well written and it's been a great resource.

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You're welcome.

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Unfortunately for me, I'm having some issues getting the jtag-to-Avalon-MM bridge to work on a Altera Stratix IV dev board, 530 edition. I'm able to get everything to compile, and everything passes in simulation. However, after programming the FPGA, and using quartus_stp to issue commands from Figure 15, I get the following error:tcl> jtag_write 0 0 0x23

Error: incorrect number of response bytes!

Everything up to that point works. The jtag_open, jtag_print_hub_info and jtag_print_node_info all produce the expected result.

Do you have any ideas what could be going on here?

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Any reason why you're using quartus_stp? If you are just using the command line, then SystemConsole works fine. I was using it today on the 230K version of the same board.

I won't be at work tomorrow, but I'll see if I can find the issue with quartus_stp on Friday.

For now, why not try using SystemConsole - look at the jtag_cmds_sc.tcl scripts in the boards area.

Which version of Quartus are you using?

Cheers,

Dave

I don't have a good reason not to use SystemConsole. And so I just tried it, and works like a charm :)

For the sake of others who may wonder, I tried both Quartus 11.1sp1 and 12.0sp2. Both worked equally well.

Thanks for the help!

Omid

Very useful tutorial!

Thank you very much.

M.

Hi Dave,

How come that System Console and quartus_stp are so slow?

To write the online ram from 0 to 3FF, takes about 27 seconds.

Is there a way to speed this up?

Or is this because of how System Console and quartus_stp are written?

For comparison, a competitor vendor of PLDs does the same in less then 1 second.

Rgds,

Kimberley

Hi Kimberley,

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How come that System Console and quartus_stp are so slow?

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If you look in the JTAG-to-Avalon-MM/ST analysis document ...

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf

You will see that the JTAG interface uses a 6MHz clock, and 8-bit byte-mode transfers occur in about 10 clocks, i.e., the best data rate you can achieve is about 600kbits/s.

The master_read/write_8/16/32 Tcl procedures only transfer one item of data at a time. Higher performance is achieved using master_read/write_memory routines. To use those Tcl procedures, you need to split your read write data into lists of bytes.

Try modifying your code to use those Tcl procedures. If you cannot get it to work, let me know, and I'll write some test routines for you.

Cheers,

Dave

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The master_read/write_8/16/32 Tcl procedures only transfer one item of data at a time. Higher performance is achieved using master_read/write_memory routines. To use those Tcl procedures, you need to split your read write data into lists of bytes.

Try modifying your code to use those Tcl procedures.

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Hi Dave,

I did modify the code and it works super with master_write_memory.

Thanks again, your a great help.

Rgds,

Kimberley

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I did modify the code and it works super with master_write_memory.

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Awesome :)

Cheers,

Dave

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How come that System Console and quartus_stp are so slow?

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If you're using a recent version of ACDS then SystemConsole provides the master_write_from_file command which is even faster (providing you have your data available as a binary file)

Hi wombat,

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If you're using a recent version of ACDS then SystemConsole provides the master_write_from_file command which is even faster (providing you have your data available as a binary file)

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Thanks! When was this function introduced (which Quartus release?)?

I doubt that it will be faster at the JTAG layer (since the JTAG traces show that master_read/write_memory are as efficient as possible), but at least it saves Tcl performing binary->string and string->binary conversions.

Cheers,

Dave

Hi Dave,

I have a question;

Say I take your example design with the ram, leds and buttons, and instead of buttons I use switches.

I run this design on two boards.

On one board I put the switch to high / one, meaning Master.

On the other board I put the switch to low/zero, meaning Slave.

I connect two usb-byteblaster to my pc and start System Console

Situation 1:

How do I:

- Scan for all available jtag2avalon master?

- How do I assign a tcl variable MASTER, to the board that has the switch to one? So that I can use that MASTER in my other procedures for doing master_functions. For example "lit led 0 if you are a master board"

- And the same question for the slave.

Situation 2:

This should be dynamic.

When I have this running, I want to be able to switch both boards in the other mode.

Meaning, the master becomes slave, and the slave becomes master.

I would like to run the same script without modifying it, and detect the new master and new slave board. Is that possible?

Situation 3:

Now I start debugging, and add sometimes a NIOS with a jtag_uart, sometimes signaltap, sometimes both and sometimes none.

Can this script then still identify the jtag2avalon master and detect the master board and the slave board?

I assume that the nios has certain "jtag_identifier_code", and the signaltap as well.

Rgds,

Kimberley