Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

Thanks Dave. i read through the jtag-to-avalon document and a bunch of interesting stuff on your Cobra web site. It looks reasonably easy to impletment the JTAG, but as you said, it's not really fast enough. My intention had been to put a DE0-nano on a simple mother board with an SD card for data recording and perhaps an external USB inteface if necessary, because I'd rather avoid having to lay out and assemble a complicated multi-layer board. But this project is a retrofit that has to go inside of existing electronic boxes on our sounding rocket payload, and a more careful survey of the available volume shows that while we have quite a bit of area (we had a 6x7" board there for the previous implementation), we only have enough height for a daughter board over an area that's not quite big enough even for the DE0-nano.

So my current thought is to try the new DEO-nano-SoC, which has built-in microSD and high speed USB (using 3300 OTG chip). If I remove several extraneous connectors, it will fit nicely. It has an ARM processor side, but my first thought was to keep the power consumption low by shutting down that side and just using the FPGA. On looking at the schematics, however, it appears that both the SD card and the USB are only connected to the ARM side, so I'd have to have it running. Do you have any feeling for the minimum power it might use? Our total througput is about 150 kB/s. (I have a board on order, but not in hand yet to try.) We could go as high as 2.5 watts for the board if necessary, but thermal management will be easier if we can keep it down to a watt or so.

If the power is OK, this seems to make the implementation pretty easy. The FPGA side is reduced to a few shift registers and a FIFO. For the server end of the USB link, I looked at the libusb user-level software as you suggested (turns out it's already installed on our Linux machines), and it appears pretty straightforward to use for what we need as long as the slave end responds properly. So the main part I'm unsure of is whether the Linux that comes with the SoC-nano has something like "USB_Gadget" support that connects higher-level stuff to the 3300 chip, which by itself appears to be pretty low level.

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So my current thought is to try the new DEO-nano-SoC, which has built-in microSD and high speed USB

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This is a newly released board, so the documentation on how to use it might be sparce or incomplete. Terasic have had the DE1-SoC and SoCKit released for a while though, so there should be enough examples for those boards.

Assuming the DE-nano-SoC can be powered from USB (I haven't checked), it should be worst-case 5V@500mA, i.e., 2.5W. I suspect it can be made to fit within your 2.5W budget. You could always test a board to see what its power requirements are, or contact Terasic and ask them.

The fact that you need to use both the FPGA and USB makes the DE0-nano-SoC sound like a reasonable fit. The other option would be an Arrow BeMicro-SDK and use Ethernet. Its a smaller PCB than the DE0-nano, but perhaps the Ethernet connector is too large?

Cheers,

Dave

I use Quartus 15.0.1 and Modelsim 10.3d. I tried to redefine VTAP as dut.jtag_master.jtag_phy_embedded_in_jtag_master.node but still failed to load the design qsy_system_jtag_master_tb.sv. Does anybody know to fix this problem?

Thanks

Tim

Hi Tim,

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I use Quartus 15.0.1 and Modelsim 10.3d. I tried to redefine VTAP as dut.jtag_master.jtag_phy_embedded_in_jtag_master.node but still failed to load the design qsy_system_jtag_master_tb.sv. Does anybody know to fix this problem?

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I suspect Altera has changed the internal implementation of their components (yet again), so the path to the JTAG tasks has changed. To determine the correct path, you could look at the code, but that is tedious ... the quick solution is to use vim to load just the Qsys system (rather than the testbench), and then use the Modelsim GUI to navigate down the component hierarchy. Once you find where it no longer matches the testbench, you can fix the path in the testbench code.

If you cannot figure it out, let me know, and I'll take a look.

Cheers,

Dave

Hi Dave,

Thanks for your suggestion. I fixed the problem after I changed VTAP with dut.jtag_master.jtag_phy_embedded_in_jtag_master.genclk1.node in tb.

Regards,

Tim

Hi Tim,

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Thanks for your suggestion. I fixed the problem after I changed VTAP with dut.jtag_master.jtag_phy_embedded_in_jtag_master.genclk1.node in tb.

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Glad that you managed to fix it!

Cheers,

Dave

Hi Dave,

thanks for this tutorial on how to use the JTAG Avalon MM Bridge without system console.

I would like to use the jtag_client to test functionality on our custom board that contains 2 FPGAs connected with a 2 lane transceiver link. The one FPGA is a Cyclone V SX means that I have a HPS system running Linux that can be used to act as avalon master in order to control my custom components.

The other FPGA is a GX device that should act as co-processor for the SX and data will be transmitted between both withe the aformebtioned transceiver link.

Now, I'm looking for a way to access this GX device with your jtag_client implementation. I successfully startet the tcl version and also compiled the little C applikation.

In both approaches, I'm missing the possibility to tell which device on the JTAG bus I would like to actually talk to.

Is there a way to do this?

Maybe to clarify what I mean:

when I run jtagconfig -d, it shows this:

developer@ad-rts-devel:~/altera_jtag_to_avalon_mm_tutorial/tcl/jtag_client_server$ jtagconfig -d

1) USB-Blaster [1-2]

4BA00477 SOCVHPS (IR=4)

02D020DD 5CSEBA6(.|ES)/5CSEMA6/.. (IR=10)

Node 30006E00 SignalTap# 0

Design hash 3BFD7E53824943D21A48

02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/.. (IR=10)

Captured DR after reset = (4BA0047702D020DD02B030DD) [96]

Captured IR after reset = (155555) [24]

Captured Bypass after reset = (0) [3]

Captured Bypass chain = (0) [3]

JTAG clock speed 6 MHz

Now, I would like to access the device with the ID "02B030DD 5CGTFD7(B5|C5|D5)/5CGXBC7B6/.. (IR=10)" with your jtag_client script or application.

I'm sorry, if you already mentioned this in your documentation, but so far I havn't found that information myself.

Regards,

Maik

Okay, sorry, I think I got it.

It does not finally run which maybe because I have not finished my FPGA configuration, but I think I understand how it should work:

I first have to start the jtag_server.tcl and after that I can use the jtag_client.tcl to access the JTAG to Avalon Master Bridge in my FPGA design, right?

And in order to get the server connected to the desired device on my JTAG Chain, I have to edit the jtag_open function and use device 2 instead of 0, right?

After that I should just be able to access the avalon slaves via JTAG in my FPGA with the jtag_client software, right?

Regards,

Maik

Hi Maik,

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I first have to start the jtag_server.tcl and after that I can use the jtag_client.tcl to access the JTAG to Avalon Master Bridge in my FPGA design, right?

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Yes. I'm pretty sure I made the client as simple as possible, i.e., if the server was not there it does not keep retrying the connection. You could easily add retry functionality, but I would recommend putting a delay in between retries.

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And in order to get the server connected to the desired device on my JTAG Chain, I have to edit the jtag_open function and use device 2 instead of 0, right?

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The indexing starts from 0, and since you want to access the second device, you will want index 1.

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After that I should just be able to access the avalon slaves via JTAG in my FPGA with the jtag_client software, right?

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Yes, that sounds correct.

Cheers,

Dave