Honored Contributor
Honored ContributorWhat an excellent tutorial! Immensely useful!
Just a couple of thoughts/questions... 1) Not sure if the term 'BFM' is an industry standard, but even Avalon's Verification IP document doesn't list what it stands for. The only thing I could see is "Bus Functional Model" is this correct? 2) In section 3.5.1, it says the test_bench generated by Altera is not recommended, in favor of the custom 'sopc_system_bfm_master_tb.sv'. Any pointers on the thought process when designing that file? Similarly for the contraints file called in the synthesis script. 3) Regarding simulation, isn't the Avalon-MM Master BFM a subset of the JTAG-to-Avalon-MM Master? If so, aside from running slower, wouldn't running just the single JTAG-to-Avalon-MM Master simulation cover JTAG and the Avalon-MM, and be closer to how the real application operates? 4) Section 4.2 says that using verilog specific includes is bad practice because among other reasons it's synthesized over-and-over even though it never changes, but in Section 4.5.1 it says that copying the library source into the working project folder is also disadvantageous... wouldn't that be solving the 'include' issue? 5) Finally, if a system already has a MM master (i.e. a soft processor), does the inclusion of the JTAG master cause potential access issues? Especially if for example an avalon slave is running from a clock that is not the same as the jtag_master peripheral? I would also imagine that if using the jtag for debugging nios code, then the quartus_stp / jtag client cannot be run simultaneously, correct? Thanks again for making a great tutorial!!
