New ContributorTurbo IP Core Tail/Trellis Termination
The user guide (https://www.intel.com/content/www/us/en/programmable/documentation/dmi1436868893828.html) for the Turbo IP core does not list any information about tail/trellis termination bits. When I simulate the encoder I get a 3-value tuple for 4 cycles at the end of encoded frame, which corresponds to the expected 12 tail bits. However, I would normally expect this to be a 4-tuple (systematic tail, parity tail, interleaved systematic tail, interleaved parity tail) for 3 cycles to get 12 tail bits. There is no description in the user guide as to how the 4-tuple is multiplexed onto 3 outputs for 4 cycles. I'm currently assuming the automagically come out in the correct order if I serialize them from 0 to 2 for over 12 cycles. I can't verify this to be true though, as the tail bits generated by this core (encoder) only match for 3 of the 4 tuples against several MATLAB 3GPP encoders.
