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Altera_Forum
Honored Contributor
14 years agoTSEMAC SW reset bit never cleared CIII+KSZ9021GQ
Hi! I have my board with CYCIII + 2 PHY KSZ9021GQ. During debugging web_server under NIOS i have error out "TSEMAC SW reset bit never cleared!". And correspondingly does not start web...
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- Hm, nothing special here... Check differences in MDIO registers between 88E1111 and KSZ9021. E.g. check if software reset bit is in the same place? P.S. I suppose ethernet is not working right? --- Quote End --- Hm, i think software reset it is register of TSE IP? Embedded Peripherals IP User Guide Table 25–7. Control Register SW_RESET Software can reset the core by writing to this bit twice. Upon the second write, the core is reset. The logic which sequences the software reset process then resets itself automatically. Executing a software reset when a DMA transfer is active may result in permanent bus lockup until the next system reset. Hence, Altera recommends that you use the software reset as your last resort.