TSEMAC SW reset bit never cleared CIII+KSZ9021GQ

If that description is correct, I don't think it is valid to wait for it to be cleared.

The clock on the MII interface is generated by the PHY, and its speed depends on the negotiated link speed. In the absence of a cable (etc) this clock is very likely to be stopped - so the current rx/tx can never complete.

You either need some more robust 'hardware reset', or be willing to leave the MAC unit 'in reset' until the PHY has finished negotiating the link speed (etc) with its peer.