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MRigh4's avatar
MRigh4
Icon for New Contributor rankNew Contributor
5 years ago

TSE SGMII autonegotiation fails and link goes down after ethernet cable connection

Hello, I instantiated the variation "10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS" IP variation of the Triple-Speed Ethernet Intel IP core. I configured the PCS registers as suggested in...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Marco,


As you are facing system level failure, hence it's hard to tell which path went wrong in the first place.

  • Is it FPGA design ? On board PHY chip configuration ? your board setup issue ? or the destination Ethernet port or equipment issue


May I suggest you start with something simple to slowly isolate the failure


Thanks.


Regards,

dlim



MRigh4's avatar
MRigh4
Icon for New Contributor rankNew Contributor
5 years ago

Thank you for the answer dlim.

It is a FPGA design, completely HW based, without NIOS processor. VHDL FSMs configure both the PHY and the TSE.

Actually it seems to be a system level issue. I tried to understand this behaviour for a week without success. During all my tries, for some reasons I also tried to connect the board to another ethernet device (is the USB docking station of the PC, with a ethernet interface) and it seems that the autonegotiation issue is not present here. I can transfer packets from PC to FPGA and viceversa.

Now I think that the problem is relevant the autonegotiation phase between the TI PHY and the external device... and not relevant the configuration of the TSE so I don't think that a simulation of the TSE would help but I'm still trying to figure out a solution.

If you have other suggestion, I will appreciated it.

Thank you,

Marco.