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I don't think that you need to edit anything in the generated sdc file. However the interface to the PHY chip isn't constrained by that file, and you need to do it yourself.
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Thanks. I tried to do it but my design still doesn't work. I'm going to be very depressed for this. What made me concerned about timing is a message I got in the "ignored constraints" in TimeQuest. There is a list of "clock creations" commands that comes from tse_constraints.sdc. I'm not an expert in this kind of architecture so my only way to debug by now was trying to run a simple_socket_server application. From NioS side everything seems to work, but I can't reach the erver anyway. DO you have a suggestion to me to break
the chain and investigate this problem?
I'm using TSE in RGMII mode.
Thank a lot.
Honored Contributor
