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Altera_Forum's avatar
Altera_Forum
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15 years ago

TSE-SGDMA something wrong

Hi all, I'm working on a custom board with nios2 + tse (10/100/1000) + DDR sdram... I'm trying to use a driver for triple speed eth under u-boot...the driver has been already tested on an altera...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear all,

can someone, please, summarize the steps that must be followed in timing constraining a design that include a tse?

I guess that tse_timing_constraint.sdc must be added in the timing analyzer sdc file list, but what must be done then?

Is there something more that must be constrained? is there somenthing that must be edited in the tse-*.sdc file?

Thanks A lot.