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Altera_Forum's avatar
Altera_Forum
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15 years ago

TSE-SGDMA something wrong

Hi all, I'm working on a custom board with nios2 + tse (10/100/1000) + DDR sdram... I'm trying to use a driver for triple speed eth under u-boot...the driver has been already tested on an altera...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You must be absolutely sure that the MAC and PHY use the same clocks. In MII mode the PHY is giving both the transmit and receive clocks to the MAC.

In RMII mode an external 50MHz clock source provides the reference clock to both the MAC and the PHY.

Some PHY have options to synchronize the data pins with the centre of the clock signal instead of the rising edge. This can help too but as long as you constrain your interfaces properly it shouldn't be a problem.