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Altera_Forum's avatar
Altera_Forum
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15 years ago

TSE-SGDMA something wrong

Hi all, I'm working on a custom board with nios2 + tse (10/100/1000) + DDR sdram... I'm trying to use a driver for triple speed eth under u-boot...the driver has been already tested on an altera...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Maybe we found the question....I've noticed that in the demo (that uses the same PHY but different interface RMII) the clock that should be coming from the PHY is instead generated internally from the PLL....this seems strange but should be reasonable considering that niosII and Phy are feeded by the same external oscillator...

Carlo