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Altera_Forum
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15 years ago

TSE-SGDMA something wrong

Hi all, I'm working on a custom board with nios2 + tse (10/100/1000) + DDR sdram... I'm trying to use a driver for triple speed eth under u-boot...the driver has been already tested on an altera...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi Daixiwen..thanx for you reply....now I'm enabling loopback on mac to check problems with phy....

Phy is a more than standard DP83848C (that I've already on the demo and is working well)..interface is MII..I don't think that more than a reset and autoneg enable is needed...(anyway I see link going up correctly...)

I have some doubt on the clock constraint...I don't remember but someone told me that the sdc automatically generated for tse doesn't constraint the 25 mhz input clock....am I wrong??

The only problem I can think about is a timing violation...

Any idea???

Carlo