TSE or SGDMA related problem with concurrent tx and rx

Found the problem cause!!!

But now I really need help from you expert guys.

Actually there's a bug in the RMII2MII block supplied with the dev board; I attached the vhd file.

The block defines two internal signals rx_clk and tx_clk but there is some sort of synchronization issue with rx_clk: the block restarts it when an input frame is received (triggered by crs high) but this clk is also used as output clock for the tse mac.

Depending on frame arrival time (crs on) the mac_rx_tx_clk will go half period out of phase (then the frame error) or remain in phase with tx_clk (no error case)

I don't know much of MII interface; can anyone suggest me how can I modify the vhd code to fix the bug?

Or better: Are there any other RMII2MII converters available?

Thank you

Cris