TSE or SGDMA related problem with concurrent tx and rx

Thank you for the answer

I had just made what you suggest and I discovered it's probably related to noise. IMHO is not related to fpga but to ethernet phy.

I'm using a DBC3C40 dev board which have a National DP83640 phy.

I monitored the CRS signal and I see that when I get the rx error CRS goes low before the complete frame has been received. When tx and rx frames don't overlap CRS behaves correctly, as far as I could test.

This is the timing:

time 0: start transmission of tx_frame

time 640ns: start receiving rx_frame (crs goes high)

time 5.36us: end of tx_frame

time 6.32us: end of tx_frame

When the frame is correctly received from my application, crs goes low at time 6.32us. When I get the error, crs goes low at time=2.40us (this is quite deterministic).

I changed the ethernet cable but the behaviour is always the same. On the dev board there's a second DBC3C40 device available and I could try to switch the design on this one. Anyway I'd like to understand why it fails