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Altera_Forum's avatar
Altera_Forum
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15 years ago

TSE MAC in mode RGMII

Hello,

I have a design in Stratix IV that uses TSE MAC in mode SGMII.

This design has been ported to Arria II GX, because i do not have any Stratix board.

My kit Arria II GX has a PHY that works only in the RGMII mode.

Since i try to change TSE to RGMII mode and do the Synthesis, i have a message like that:

Error: Input port DATAIN of DDIO_IN primitive "Nios2DPX_example_system_top:top_inst|Nios2DPX_example_system_top_tse:tse|altera_tse_mac:altera_tse_mac_inst|altera_tse_top_gen_host:top_gen_host_inst|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_d1e:auto_generated|ddio_ina[0]" must come from an I/O IBUF or DELAY_CHAIN primitive

Do you know what it means?

The reference design has many pins that are not used, like mem_dq, mem_ba, mem_dqs... and I dont know if there is some connection between the problem and this pins.

I really appreciate your help in this question..

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I'm not sure which example design you are looking at.

    Also, which release version are you using? There are 9.1.2 and 10.1.

    In the bts_config design, there shouldn't be those memory pins in the top RTL.

    It is using RGMII for the ethernet.

    I don't think there is any relation with memory pins.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    hi guys ......

    the SGMII transmit data in serial mode to phy .....

    RGMII use paralell mode ( 4 pins data[0] to data[3] )....you need to conect the data pins to phy .........

    isnt difficult to chage modes....

    cheer

    Franz Wagner
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hy!

    Thank you for your answers..

    I now trying to port the design to Arria bsed on this reference design:

    nios ii ethernet standard rgmii design example (altera wiki)

    It uses Arria II GX with TSE in RGMII mode.

    So, the problem with ddio is solved. There is an instance of alt_ddio in the design top level.

    But I have a problem yet.. Altera recommends to change configure software in Nios II SBT for RGMII mode. There is a link in the altera wiki that goes to

    the support question:

    how do i change the nios ii triple speed ethernet mac drivers to use rgmii settings?

    In my case, Im not using TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO

    and I dont know how to configure this..

    Im trying:

    alt_tse_system_info tse_mac_device[MAXNETS] = {

    TSE_SYSTEM_MAC(TSE_MAC)

    TSE_SYSTEM_PHY(TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii)};

    Could anyone help me on this?

    Thank you very much

    Emanuela
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    hi.......

    you can use normaly TSE in RGMII mode .........

    you only need to do a vhdl or verilog module to adapt the signals...........

    rgmii use 4 pins and gmii use 8 pins ......... your work is do that.......

    cheers

    Franz Wagner