Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorTSE MAC catatonic
I've got a real head-scratcher of a problem with the Altera TSE MAC core. Here's the outline: * Altera/Terasic DE2-115 board, Cyclone IV-E FPGA * Full Quartus subscription, but no TSE license...
Altera_ForumHonored Contributor
Honored ContributorI wonder if you could "fix" this problem by polling the DMA status just once, after having cleared the IRQ. It should be enough to ensure that you don't miss any completed descriptor.
Of course a more elegant way would be to have a clear IRQ signal on each descriptor rather than in a common register, so that any unprocessed descriptor would still raise the IRQ. I don't know how much modifications to the mSGDMA code would be required, but BadOmen should have a good idea about this I guess.
