TSE MAC catatonic

That's odd, it seems that something gets stuck inside the TSE core. But at least the fact that the octets counter increases shows that the opencore evaluation is still running.

I don't remember if this is possible with the small TSE core, but can you disable CRC checking?

Are the clocks correctly connected between the TSE core and the PHY chip?

Does the hardware design complies with all the timing requirements?

If you could replace the DMAs with Altera's SGDMAs and try to run a standard software example with uc/OS and Niche stack (such as the sockets server example) you could check if this as a hardware of software issue.