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Altera_Forum's avatar
Altera_Forum
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14 years ago

TSE MAC cannot give gm_tx_d on board.

Hi, all,

It is the first time I use the TSE MAC.

My target is to run TSE MAC on a Stratix IV GT Evaluation Board without the Nios II.

I'm a beginner on FPGA coding, and I like to use the schematic input and Vector Waveform File for simulation.

The followings are what I have done, and the problems I have.

1. Packet generator accomplished

Based on tse_datapath_reference_design

Avoid CRC

Function works normal in all following cases

2. 10/100/1000 Mb Ethernet MAC

Megawizard Plug-In Manager

Study all the input and output

tx_clk, rx_clk =125MHz for Triple-Speed

ff_tx_crc_fwd=0, MAC generates the CRC

3. Packet generator + MAC 1000M

Quartus II 8.0 32bit, EP3C40F484C8 (Cyclone III)

Quartus II 8.0 32bit, EP2SGX90EF1152C3 (Stratix II GX)

Quartus II 9.1 32bit, EP2SGX90EF1152C3

Built-in simulater (vwf input)----Quartus II 10 and 11 cancelled this simulater, and I do not know to make a simulation with ModelSim-Altera

MAC gm_tx_d miss the first 16bits of the packet----I do not know why, and do not know where to begin to analyze this problem.

4. Packet generator + MAC 1000M

Quartus II 11 32bit, EP2SGX90EF1152C3 (Stratix II GX)

Quartus II 11 32bit, EP4S100G2F40I2 (Stratix IV GT?)

Signaltap II on Evaluation Board

MAC gm_tx_d no output----I got mad by this problem. I do not why there are no outputs when I used the Signaltap II.

Please help me, any suggestion or hints. Thank you.

Futian

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I would suggest using SOPC builder for TSE MAC instantiation, so You could avoid setting up PHY management stuff.

    The first 16bits are removed due to 32bit boundary align setting in TSE MAC core settings.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I would suggest using SOPC builder for TSE MAC instantiation, so You could avoid setting up PHY management stuff.

    The first 16bits are removed due to 32bit boundary align setting in TSE MAC core settings.

    --- Quote End ---

    The only thing I know about the sopc is from the lab course in collage. Can I use the sopc without a nios ii core? And the code running on the core? I do not what to add too much things into my design.

    And about the missing 16 bits, is that ok if the first 16 bit of the destination mac? (The missing 16 bits seems not the really part of the mac.) If not, how can I get it back by the sitting of the tse mac?

    Thanks again.

    Futian
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I solve the problem of no output on gm_tx_d, it is because of the TSE MAC configuration. It failed when I use my logic to write the config.

    My initialization logic works well in the simulator, but when on board, the TSE MAC cannot take the config "write" signal well. When I modify the logic, slow it down, the TSE begin to work. But the PHY chip on board is still not working.