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Altera_Forum's avatar
Altera_Forum
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12 years ago

tse ip core communicate with pc

hi, I instantiate the tse ip core with configuration of 10,100/1000Mb mac and RGMII interface in my project to communicate with pc,then initialize the register space of mac with the recommended ini...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Yes it is those clocks that you need to check. As for the rx signals on the RGMII side, you should see activity on those when the PHY receives a packet.

Are you using the Altera drivers? Could you show the exact output you get on the console?

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sorry，what do you mean the Altera drivers? I have checked the clocks of clk(50mhz),ff_tx_clk(125mhz) and ff_rx_clk(125mhz) which are woring normally! But the mac still can't reset properly.I will show you the signaltapII results in attachments for you.