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Honored Contributor
Honored Contributortse ip core communicate with pc
hi, I instantiate the tse ip core with configuration of 10,100/1000Mb mac and RGMII interface in my project to communicate with pc,then initialize the register space of mac with the recommended ini...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- No wait, I'm sorry, I wrote something wrong. The clocks that you need to check are the ones on the Avalon Stream interfaces, so on the other side of the TSE. It is those clocks that need to be active for the TSE to reset properly. --- Quote End --- sorry!Do you means the check of clocks of ff_tx_clk,ff_rx_clk and clk?These clocks are working correctly,but i don't know how can i make the rx_clk,rx_control and rgmii_in interfaces work correctly?
