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Honored Contributor
Honored ContributorTSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock
Hi everybody, I try to use the Altera TSE in SGMII Mode with external FIFO. My board is a SoCKit. I need a 125 MHz signal for the pcs_ref_clk and want to keep it simple and do not change the SI533...
Altera_ForumHonored Contributor
Honored ContributorI don't want to hijack this thread if the issue has not been resolved, but I am also trying to utilize the HSMC_REF_CLK (at 100MHz) for the same exact task (to feed the TSE). My issue, however, is that I am not even getting a clock signal from the HSMC_REF_CLK (I'm using Pin 9 as an input into my design which, according to the schematic, is the HSMC_REF_CLK). For the OP or anyone else who can answer, did you have to do any set-up with the 5338 to get this signal to work? Or are you just using it as you would any other clock signal (e.g., the 50 MHz clock, which works just fine)?
Note: I have never used a diff pair clock signal before, so perhaps my design is flawed? Thank you!
