TSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock

Thanks for your reply.

Yes, the SoCKit has a Cyclone V on it. Maybe it is because I am very new to Quartus: What do you mean by "use a PLL on the same side of the device as the transceiver"? Is there a way to use a certain PLL?

It says that I am using 1/15 PLLs, so this is not a limitation of PLLs but maybe a limitation of paths? I can not find a value about clock control blocks.

Well, I need to say that I maybe miss a important part and why the title says "with external FIFO":

If I use the internal FIFO, it works with a PLL. In the near future I want to use multiport TSE that is why I am not using internal FIFO anymore.

To summarize:

internal FIFO:			hsmc_ref_clk => pcs_ref_clk			OK (but wrong frequency)
				hsmc_ref_clk => PLL => pcs_ref_clk		OK
external FIFO:			hsmc_ref_clk => pcs_ref_clk			OK (but wrong frequency)
				hsmc_ref_clk => PLL => pcs_ref_clk		Error seen in the first post

The only combination which is not working is the one I need :D