Forum Discussion
Deshi_Intel
Regular Contributor
4 years agoHI,
Typical FIFO design should contains its own threshold setting like full or empty to prevent overflow or underflow situation. (aka back pressure flow control)
If you are using TSE IP internal FIFO then it contains even more threshold control mechanism as shown in chapter 4.1.6. FIFO Buffer Thresholds (page 46).
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
- Pls check out the TSE user guide chapter 4.1.6 for more detail
Thanks.
Regards,
dlim