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Altera_Forum
Honored Contributor
16 years agoTSE ff_rx_data problem
The data I actually sent to the board is : 0000 ff ff ff ff ff ff 00 1d 7d 75 c4 24 08 06 00 01 ........}u.$.... 0010 08 00 06 04 00 01 00 1d 7d 75 c4 24 c0 a8 01 07 ........}u.$.... ...
Altera_Forum
Honored Contributor
16 years agoHi Dai.
The first two bytes of "O" is indeed because of the alignment, and the those bytes of "O" s at the end is padding, to fill up the minimum length of the frame. you told me to check the rx_err signal, unfortunately my rx_err pin has been buried under the 88e1111 fbga and left floated. I thought rx_err was no use in RGMII mode. But now I am in the so called 88e1111 Modified MII mode, I really don't know how to check the rx_err in such case, I haven't found the answer from datasheet. But since now the ff_rx_data is correct, I can just ignore this problem. ----------------------------------------------------- Now I've been trying to send data to PC for two days, and never worked it out. The attached jpeg is PHY tx_en & txd[3:0] signals. the preamble is 7 bytes 0x55 , sfd is 0x5d. (Note: I've never put preamble,sfd and crc data in to the tx fifo, I don't know weather they are generated by TSE or PHY.) Then followed by 60 bytes of 0xa5, and ends with 4 bytes of CRC. The total packet length is 64 bytes, not including preamble and sdf. All seems to me are correct, but I still can't sniff the packet from PC. And about enabling the internal CRC module of TSE core, I can't find this option in the core parameters, I am using TSE core v7.2.