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Altera_Forum
Honored Contributor
16 years agoTSE ff_rx_data problem
The data I actually sent to the board is : 0000 ff ff ff ff ff ff 00 1d 7d 75 c4 24 08 06 00 01 ........}u.$.... 0010 08 00 06 04 00 01 00 1d 7d 75 c4 24 c0 a8 01 07 ........}u.$.... ...
Altera_Forum
Honored Contributor
16 years agoI think you are right Mr. Dai.
RGMII Transmit Data. In RGMII mode,. RXD[3:0] are used as RD[3:0]. In RGMII mode, RXD[3:0] run at double data rate with bits [3:0] presented on the rising edge of RX_CLK, and bits[7:4] presented on the falling edge of RX_CLK. In this mode, RXD[7:4] are ignored. In RGMII 10/100BASE-T mdoes, the transmit data nibble is presented on RXD[3:0] on the rising edge of RX_CLK. As said on ds, now the PHY is operating in 100BASE-T mode ( I don't know why, because i've set set_1000 to 1). data is presented on rising edge of clk. But what is don't understand is that when it's in RGMII giga mode. though RXD[3:0] is running at double data rate, but only bits[3:0] are presented on rising edge, and bits[7:4] which presented on falling edge are ignored. Is that means either in giga mode or 10/100 base-t mode, we can only fetch data on rising edge? If so, how come TSE would think that the PHY will give out DDR signal? I am confused, please light me.