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Altera_Forum
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16 years ago

TSE ff_rx_data problem

The data I actually sent to the board is : 0000 ff ff ff ff ff ff 00 1d 7d 75 c4 24 08 06 00 01 ........}u.$.... 0010 08 00 06 04 00 01 00 1d 7d 75 c4 24 c0 a8 01 07 ........}u.$.... ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

the link speed is 100M, and rx_clk is 25Mhz.

ff_rx_clk is 125mhz (it saids ff_rx_clk is completely independent from rx_clk).

what do you mean by the interface between TSE and PHY? Avalon-ST?

here is parameters of the core:

Core variation: 10/100/1000mb Ethernet MAC

Interface: MII/RGMII