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Altera_Forum
Honored Contributor
10 years agoHi Kkaibara,
I truly appreciate that, you helped a lot! Followed your instructions, These signals are monitored successfully. We also added timing constraints for Tx path according to "AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs" and now Transmitting data is stable. Only concern we have left - monitor on PC (we use WireShark) receive more data than TSE core statistics counters show. For example, aFramesTransmittedOk is 20.000 and WireShark somehow has 20.087. Debugging at this point. Regards, Alex