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Altera_Forum
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14 years ago

TSE 1000MHz clock phase

Hi, I use ethernet port on terasic DE3 and DE2-115, GMII and RGMII respectively. The clocks are both 125MHz, could anyone tell me any requirement for the timing shift? It seems in RGMII mode I ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

not entirely true. if it is a marvel phy, there is a mdio register that causes the phy to perform the needed clock shifts. by default, rgmii requires tx data to be center aligned, and rx data will be edge aligned, necessitating a 90deg shift for the RX data.

if you are using a more recent quartus, there is an example sw project for rgmii that sets this bit appropriately.

--dalon