New Contributor
Super ContributorHi @bob_rf
You may checkout this KDB to solve the error
https://www.intel.com/content/www/us/en/support/programmable/articles/000085676.html
The Intel FPGA IP Evaluation Mode is the right way to go as it allows you to evaluate these licensed Intel FPGA IP cores in simulation and hardware.
https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/an/an320.pdf
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
New ContributorRichardTanSY_Intel,
Thank you for replying here.
Regarding the first link you included with your message.. I had found this link during my troubleshooting. Advice from the link:
"To avoid this error, disable the EDA simulation tool in your project by opening the Settings dialog box from the Quartus II Assignments menu. Select the category EDA Tool Settings and the subcategory Simulation. On the Simulation page of the Settings dialog box, change the Tool name option to <None>."
It sounds like the suggestion here is to totally disable the simulation, you know, to get the error to go away. The error that comes up when I am trying to simulate... What am I missing here?
I tried this method before and it did not work. I follow these instructions again and I still get the same error code (vsim-3033) I listed above when trying to run a simulation in ModelSim.
Also the second link included here is busted/broken. "Oops" (from the page). Might have to do with it being a .cn link (Intel China?). I do have the .pdf for this downloaded and I have referenced it. Is there a specific section you would have me see and follow instructions on?
I did make sure the Quartus tool was set Enabled for Evaluation Mode. This appears to be the default setting. (see above picture from my Quartus Prime Lite tool)
It does not seem to make a difference in allowing the design to compile, i.e. it still cannot compile. The failure occurs at EDA Netlist Writer step (with the previously mentioned errors).
Let me know if you can think of any other advice for getting a simulation to run in evaluation mode.
Regards,
Robert
Super ContributorHi bob_rf,
Looks like modelsim can't find the "auk_dspip_r22sdf_top" module for simulation.
Try opening <your fft ip folder>/synthesis file and including the .qip file into quartus.
This included all submodules of FFT IP into quartus and do compilation again.
Probably can resolve the error.
Best regards,
Sheng
New ContributorSheng,
Thank you for reaching out to me here and for your suggestion.
I checked if I had made sure to add the .qip file(s) for using the FFT IP in my design.
I am not sure if the snapshots I included will be easy to read on your side - the purpose of attaching these is to show the .qip files look present under the Files section of Project Navigator, as well as the Hierarchy section. Simultaneously it can be seen that the EDA Netlist Writer step of compilation is incomplete, and an error such as 204009 can be seen in the terminal window.
For the record, "Intel FPGA IP Evaluation Mode" is set to Enabled.
Let me know what other problem you think it could be for me. Again, thanks for your suggestion.
Regards,
Robert
