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Honored Contributor
Honored ContributorTrouble with CIC filter
I'm trying to implement a CIC decimation filter( with R = 1000, M = 1 and N = 2 ) and Fs = 1 MHz without using the CIC IP core. Using matlab implementation I found out that the suppression of the CIC...
Altera_ForumHonored Contributor
Honored ContributorM = 1 means one stage delay. Hence you need a basic accumulator where output goes through one register back to adder. What you should remember is that a signal assignment statement inside clocked process creates a register and so you don't need extra delay
