Hello, I'm working on a simple video buffer, using the altsyncram dual port megafunction. Reading the memory works fine, I can display video using a memory initialization file. Writing to memory seems to have no effect at all. In simulation, all of the signals are in the correct places (WE is high, address and data are set and unchanged). I even tried holding the WE signal high an extra cycle. Is there something I'm missing? Is it not okay to have both ports run off the same clock? Thanks in advance

Are there clock enable or byte enable inputs that you're not asserting during writes?

--- Quote Start --- Are there clock enable or byte enable inputs that you're not asserting during writes? --- Quote End --- I don't have any extra ports enabled in the megafunction, so they should default to something useful.

If it doesn't work in simulation then you're clearly doing something wrong. If you drill down into the RAM in simulation what do you see during writes? Does everything look right at that level? There are only a few signals involved here so it's got to be a simple problem. Any synthesis warnings that might explain it?

--- Quote Start --- If it doesn't work in simulation then you're clearly doing something wrong. If you drill down into the RAM in simulation what do you see during writes? Does everything look right at that level? There are only a few signals involved here so it's got to be a simple problem. Any synthesis warnings that might explain it? --- Quote End --- I've never been able to get the ram to show data in simulation, its outputs are always Z. The input signals appear correct in simulation though, and on hardware the read functions correctly. I can't launch modelsim from quartus since it says the path is wrong even though it's correct, so it's probably not simulating the ram correctly anyway.

This should be a no-brainer. At some point you should seriously consider figuring out what the simulation problems are. That's the easiest way to resolve issues like this. Can you attach the .qip file for the RAM and the source file where you instantiate it?

Trouble with altsyncram on cyclone III | Altera Community

13 Replies

Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
It took me a lot of effort to get signal tap to actually pick something up, but when I finally did, I noticed all of the signals looked good. I then turned around and looked at the screen, and behold, the characters written to memory was displayed. Only problem is, I can't get it to work without signal tap, so I'm at a loss as to what's going on. Any ideas?
--- Quote End ---

This stuff will drive you nuts sometimes. The only thing I can think here is that one or more signals are getting optimized out without SignalTap, but when they are instrumented in SignalTap they do not get optimized out. I assume that in SignalTap you selected nets "pre-synthesis"?

If anything is getting optimized out it should be mentioned in the reports, but it sounds like you're not seeing anything? If that's the case then it might be worth trying the netlist viewers (Tools -> Netlist Viewers) to make sure everything is hooked up properly. You can look at the rtl viewer or post-map or post-fit. Try compiling without SignalTap and then find your VRam in the post-map viewer and see if it's connected correctly.

If you simply can't figure this out then it's time for a service request. That can be a frustrating process, but if you're able to send them an archived project they should be able to figure it out for you.

Good luck. Please post back with whatever you find out (hopefully with the problem resolved).

Bob
Altera_Forum
Honored Contributor
9 years ago
I finally fixed it. Some people on freenode IRC helped me out, and as far as I can tell it was a problem with the way my reset logic was written. Maybe it was metastability, along with not having negedge nReset in my sensitivity list for synchronous processes, or a combination of things, I guess I'll never know for sure.
Altera_Forum
Honored Contributor
9 years ago
Interesting problem. Never seen that one before. Glad you got it fixed, and thanks for posting back!

Bob

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Trouble with altsyncram on cyclone III

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